What is it?
The MR68K0 – or the Mercury RISC 68K, revision 0 - is a custom designed CPU implemented in an FPGA which is compatible with a streamlined version of the Motorola 68K instruction set. The “streamlining” involves moving the original ISA to be more RISC-like in that the memory direct addressing mode is stripped out. Therefore code resembling:
add.l [d1], [d2], d3
becomes something like:
mov.l [d1], d4
mov.l [d2], d5
add.l d4, d5, d3
(It's been awhile since I looked over the 68K assembly, so forgive my hastily generated code.)
One may think this serves no purpose other than to stretch one operation out into three, thereby making things actually run slower, however this is not the case. Now that one instruction is broken down into three, a clever programmer (or a craftily designed compiler) can now interleave other instructions between these three and make use of unused portions of the CPU which would otherwise be sitting idle. Also, each of the three RISC instructions takes less time and CPU resources to execute, further improving overall processor performance.
Why would you want to do that?
The short answer is that the Intel x86 ISA sucks. No, seriously. It's built on kludge after kludge to support ancient 16 bit code, a modern memory protection scheme and cutting edge 64 bit code. Even if that were necessary for modern systems – in this modern age of UEFI and 64 bit operating systems, it's really not – it could have been done in a much more cohesive manner. The obvious alternative is the 68K line of processors, however they, as luck would have it, are no longer in production. Although it is quite powerful, even the most recent member of the 68K family – the 68060 - isn't that impressive compared to modern chips at its factory rated top speed of 75 MHz, albeit some users hitting 105 MHz on certain mask revisions. And sure, you could just a more modern QUICC, ColdFire or DragonBall processor, but those aren't really direct descendants of the venerable 68K line. This project is intended to be an optimized version of what Motorola may have made after the 68060 had they not abandoned the 68K architecture for the then-revolutionary PowerPC.
What are the specs?
-Target speed of 250 MHz
-Fully 32 bit data and address bus
-A total of 32 registers, each 64 bits wide
-Instructions now work in 64 bits
-CPUID instruction (Finally!)
-Custom processor intercommunication bus
-16 stage instruction pipeline
-Dual instruction and data caches, each 64K in size
What's the progress?
So far... none. This exists only in my head, and now here in pixels. I do, however, have an FPGA expert lined up with whom to discuss things, and after work is finished on the EPiC Mini I intend to proceed with this design - if it is in fact feasible - to use as the CPUs of the multiprocessor EPiC computer – a.k.a. the Mini on steroids. :)